The demand for more powerful computers and communication products has resulted in faster processors that often consume increasing amounts of power. However, design engineers struggle with reducing power consumption, for example, to prolong battery life, particularly in mobile and communication systems.
Communication products and computers utilize memories to store a variety of different information. For example, some information is temporary in nature because once the particular application is completed the information is no longer needed, thus, it is designated as a working storage data type. In contrast, some information is needed indefinitely or for a long-term, such as, application programs and utilities, and is designated a long-term data type.
A Dynamic Random Access Memory, DRAM, is a typical memory to store the previously described information types. DRAMs contain a memory cell array having a plurality of individual memory cells; each memory cell is coupled to one of a plurality of sense amplifiers, bit lines, and word lines. The memory cell array is arranged as a matrix of rows and columns, and the matrix is further subdivided into a number of banks.
The DRAM memory cell consists of a single transistor and a single capacitor and is dynamic because charge stored on the capacitor decays because of a various leakage current paths to surrounding cells and to the substrate. Typically, a refresh operation is performed on the DRAM memory cell to ensure the validity of the data. For example, the refresh operation is initiated by a memory controller to read the data from the cell array via the sense amplifiers and subsequently rewriting the data back into the cell array. Thus, the refresh operation restores the capacitor""s charge to ensure the validity of the data.
Typically, Synchronous Dynamic Random Access Memories (SDRAMs) can support a self-refresh, which is a refresh operation executed by the SDRAM rather than the memory controller. During the self-refresh, the SDRAM utilizes an internal oscillator to generate refresh cycles to maintain the data in the memory cells. Presently, a low-power SDRAM allows for a subset of the memory to be refreshed with a partial-array self-refresh feature. For example, the partial-array self-refresh (PASR) feature for a four bank SDRAM allows for one, two, or four banks to be refreshed.
Typically, self-refresh features are not fully utilized to ensure a reduction in system power consumption because the SDRAM refreshes all the data, regardless of the data type.